The present invention relates to a semiconductor memory device. More particularly the present invention relates to a semiconductor memory device that allows for a direct current (DC) voltage test after packaging.
Recently, semiconductor memory devices have been designed to provide higher integration, multiple functions, and lower power dissipation. In response to these trends, the number of bonding pads 20 used to control a semiconductor device 15 have increased, as shown in FIG. 1. This larger number of bonding pads 20 allows for high integration and multiple input and output functions. In addition to an increase in the number of bonding pads 20, the number of DC voltage generators 10 of differing voltage levels in the semiconductor device 15 has also increased, resulting in an increase in the number of checking pads 22 required to check the voltage levels of these voltage generators. These DC voltage generators 10 are required for controlling power in the semiconductor device 15, but the addition of the checking pads 22 serves to undesirably increase the chip size.
The checking pads 22 can be used to perform electrical tests regarding the status of the semiconductor deceive 15 when they are linked to probes connected to electrical test equipment. However, the DC voltage level of each checking pad 22 cannot be measured before the checking pads 22 are bonded with package leads, and so cannot be measured until the wafer assembly of the semiconductor device 15 is completed. As a result, it is extremely difficult, if not impossible, to find out how the assembly process in particular impacts on the DC voltage levels measured once the wafer is fully assembled.
Furthermore, the addition of more checking pads 22 to measure the DC voltage of the packaged semiconductor device 15 entails an undesirable increase in chip size and cost.